The present invention relates to a large scale integrated circuit for use in a computer, and in particular, to a method of controlling a high-performance cache memory implemented by use of an external memory chip.
In regard to a cache memory of the prior art, as described in JP-A-1-226053, there has been known a central processing unit (CPU) to be employed in a computer having a write-through cache memory. In this configuration, when data is written into the cache memory, the data is also stored in a storage buffer to be used in a first-in first-out processing system so that while a write operation is being processed, the computer executes a subsequent instruction without waiting for completion of the write operation.
In the conventional technology above, since a write port disposed to write data in the storage buffer and a port used to read data from the storage buffer so as to write the data in the cache memory outside the CPU have an identical data width, it is difficult to increase the throughput of the write operation in the cache memory. Consequently, when the quantity of data to be written in the store buffer by the CPU is increased as compared with the throughput, there appears a state where the storage buffer is continuously full of data, that is, free areas cannot be found therein. As a result, the storage buffer cannot function as a buffer, which leads to a problem that the throughput limits the processing speed of the CPU and hence lowers the performance efficiency thereof.
Furthermore, according to a system described in JP-A-61-223956, two entry items are simultaneously read from a storage buffer and then the respective addresses thereof are compared with each other to control a write operation in a storage based on a result of the comparison.
In the system of JP-A-61-223956, although the throughput of the write operation is improved to a certain extent, it is restricted to the cache where the entry items are ordinarily assigned with an identical address.